Abstract

Dynamic cache reconfiguration (DCR) is an effective technique to optimize energy consumption in many-core architectures. While early work on DCR has shown promising energy saving opportunities, prior techniques are not suitable for many-core architectures since they do not consider the interactions and tight coupling between memory, caches, and network-on-chip (NoC) traffic. In this article, we propose an efficient cache reconfiguration framework in NoC-based many-core architectures. The proposed work makes three major contributions. First, we model a distributed directory based many-core architecture similar to Intel Xeon Phi architecture. Next, we propose an efficient cache reconfiguration framework that considers all significant components, including NoC, caches, and main memory. Finally, we propose a machine learning-based framework that can reduce the exploration time by an order of magnitude with negligible loss in accuracy. Our experimental results demonstrate 18.5% energy savings on average compared to base cache configuration.

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Citation

@article{charles2019efficient,
  title={Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPs},
  author={Charles, Subodha and Ahmed, Alif and Ogras, Umit Y and Mishra, Prabhat},
  journal={ACM Transactions on Design Automation of Electronic Systems (TODAES)},
  volume={24},
  number={6},
  pages={1--23},
  year={2019},
  publisher={ACM New York, NY, USA}
}